`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:31:09 04/28/2014 
// Design Name: 
// Module Name:    Frame1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Frame1(
	output 		reg	[7:0] 	color,		
	input					[10:0]	hcounter, vcounter,										
	input 				clk , clk_5Hz, blank		
				);
	
	parameter	RMh=200, RMv=50,	
					ECh=166, ECv=90,	
					PRh=140, PRv=230,	
					ENh=235, ENv=230,	
					TOh=382,	TOv=230,	
					GEh=162,	GEv=400;	
					
	
	reg	[2:0]		cc;				
	reg	[1:0]		f;
	reg 	[15:0]	addr;
	wire				data;
	
	always@(posedge clk_5Hz)										
			begin 
				if(f<3)
					f<=f+1;
				else					
					f<=0;
			end		
			
	F_ROM_1 U1(clk ,addr, data);	
	
	always@(hcounter, vcounter)
		begin 
			if (blank==0)
				begin
////////////////////////////////Rhythm Master////////////////////////////				
					if (((hcounter-RMh)<244)&&((hcounter-RMh)>=0)&&((vcounter-RMv)<30)&&((vcounter-RMv)>=0))
						begin
							cc<=3'b000;
							addr<=(vcounter-RMv)*244+hcounter-RMh;
						end	
////////////////////////////////EC551 group eagle/////////////////////////				
					else if (((hcounter-ECh)<308)&&((hcounter-ECh)>=0)&&((vcounter-ECv)<30)&&((vcounter-ECv)>=0))
						begin
							cc<=3'b001;
							addr<=(vcounter-ECv)*308+hcounter-ECh+7320;
						end	
////////////////////////////////RRESS////////////////////////////////////							
					else if (((hcounter-PRh)<95)&&((hcounter-PRh)>=0)&&((vcounter-PRv)<30)&&((vcounter-PRv)>=0))
						begin
							cc<=3'b010;
							addr<=(vcounter-PRv)*95+hcounter-PRh+16560;
						end	
////////////////////////////////ENTER///////////////////////////////////					
					else if (((hcounter-ENh)<147)&&((hcounter-ENh)>=0)&&((vcounter-ENv)<30)&&((vcounter-ENv)>=0))
						begin
							if (f<2)
								begin
									cc<=3'b010;
									addr<=(vcounter-ENv)*147+hcounter-ENh+19410;
								end
							else 
								begin
									cc<=3'b011;
									addr<=(vcounter-ENv)*147+hcounter-ENh+19410;
								end								
						end
////////////////////////////////TO START//////////////////////////////////									
					else if (((hcounter-TOh)<128)&&((hcounter-TOh)>=0)&&((vcounter-TOv)<30)&&((vcounter-TOv)>=0))
						begin
							cc<=3'b010;
							addr<=(vcounter-TOv)*128+hcounter-TOh+23820;
						end	
////////////////////////////////GROUP EAGLE///////////////////////////////	
					else if (((hcounter-GEh)<316)&&((hcounter-GEh)>=0)&&((vcounter-GEv)<30)&&((vcounter-GEv)>=0))
						begin
							cc<=3'b100;
							addr<=(vcounter-GEv)*316+hcounter-GEh+27660;
						end	
/////////////////////////////////////////////////////////////////////////	
					else 
						begin
							addr<=0;
						end	
				end
			else
				begin
					addr<=0;
				end
		end
		
		always@(posedge clk)		
			begin
				case (cc)
				3'b000:	
					begin
						color<=data?8'b00000000:8'b11111100;	//Rhythm Master  color
					end
				3'b001:	
					begin
						color<=data?8'b00000000:8'b11110100;	//EC551 group eagle color
					end		
				3'b010:	
					begin
						color<=data?8'b00000000:8'b11111111;	//RRESS & TO START color
					end
				3'b011:	
					begin
						color<=data?8'b00000000:8'b11100001;	//ENTER color
					end
				3'b100:	
					begin
						color<=data?8'b00000000:8'b11011100;	//GROUP EAGLE color
					end
				endcase
			end	
endmodule
